1. Field of the Invention
The present invention is related to design automation and more particularly to design automation tools for analyzing and optimizing integrated circuit designs.
2. Background Description
Register Transfer Language (RTL) coding plays an important role for any Application Specific Integrated Circuit/Field Programmable Logic Array (ASIC/FPGA) development. RTL coding influences the quality of device layout, design cycle time length, and design tool run time.
Typically, a designer tries to optimize the netlist results (e.g. timing or area) within the synthesis tools guided by tool dependant constraints. However, even when sophisticated synthesis strategies are used for optimization, the quality of the resulting netlist heavily depends on the quality of the RTL code (good RTL code in-good netlists out; garbage in-garbage out). Although the designer may optimize RTL code manually, besides providing individually varying results from designer to designer, such optimization is unacceptably time consuming and still error-prone. Consequently, focus mainly is directed to synthesis tools to optimize the resource sharing in a design. Unfortunately, inefficient RTL coded functions increase logic optimization time, and may still result in a less than optimal code or circuits, while simultaneously increasing design to silicon time turnaround (time) because both layout analysis and static timing analysis require additional time. Some designs may result serendipitously in silicon friendly code (producing optimum code for tool analysis and optimization) and others are not silicon friendly. However, optimizing an RTL coded design manually is very time consuming and requires training and discipline.
Thus, there is a need for RTL code optimization and, in particular for RTL code resource sharing optimization. Further, since RTL coding is a critical task for resource sharing, an automated approach is needed for such optimization.
The present invention is a system and method of optimizing a circuit design. The design may be coded in register transfer language (RTL) code. First the design code representing an integrated circuit design to be optimized is retrieved and sequentially searched for decision constructs. As each decision construct is encountered, it is checked to determine whether both branches drive a common output in response to a common select signal. If so, a determination is made whether the decision construct includes a common arithmetic operation in said both branches, and so, may be optimized. A construct library for a corresponding optimized construct and the selected decision construct is replaced with an optimized construct. After all of the decision constructs are checked, the optimized design code is stored, replacing the original design code. The optimized RTL design code has an identical logic function to the original retrieved RTL code.